Technology scalable matrix processor data par soliman mostafa (8 résultats)

Etat : New. pp. 228.

Taschenbuch. Etat : Neu. A Technology-Scalable Matrix Processor for Data Parallel Applications | Trident Processor | Mostafa Soliman | Taschenbuch | 228 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783844395327 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.…

Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book overviews VLSI technology constraints and introduces the architecture of the Trident processor, which tries to overcome these constraints and to satisfy the requirement of future applications. In addition, this book proposes the use of a multi-level instruction set architecture (ISA) to express fine-grain data parallelism to the Trident processor instead of using a huge transistor budget to dynamically extract it. Since the fundamental data structures for a wide variety of data parallel applications are scalar, vector, and matrix, our proposed Trident processor extends a scalar ISA with vector and matrix instruction sets to effectively process data parallel applications. Like vector microarchitectures, the Trident processor consists of a set of parallel lanes (each lane contains a set of vector pipelines and a slice of a register file) combined with a fast scalar core. However, the Trident processor can effectively process on parallel lanes not only vector but also matrix data. 228 pp. Englisch.…

Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Soliman MostafaMostafa I. Soliman is an associate professor at the South Valley University, Egypt. He received M.E. (1998) from Egypt and Ph.D. (2004) from Aizu University, Japan in Computer Science and Engineering. He is interest. …

Etat : New. Print on Demand pp. 228 2:B&W 6 x 9 in or 229 x 152 mm Perfect Bound on Creme w/Gloss Lam.

Etat : New. PRINT ON DEMAND pp. 228.

Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book overviews VLSI technology constraints and introduces the architecture of the Trident processor, which tries to overcome these constraints and to satisfy the requirement of future applications. In addition, this book proposes the use of a multi-level instruction set architecture (ISA) to express fine-grain data parallelism to the Trident processor instead of using a huge transistor budget to dynamically extract it. Since the fundamental data structures for a wide variety of data parallel applications are scalar, vector, and matrix, our proposed Trident processor extends a scalar ISA with vector and matrix instruction sets to effectively process data parallel applications. Like vector microarchitectures, the Trident processor consists of a set of parallel lanes (each lane contains a set of vector pipelines and a slice of a register file) combined with a fast scalar core. However, the Trident processor can effectively process on parallel lanes not only vector but also matrix data.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 228 pp. Englisch.…

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book overviews VLSI technology constraints and introduces the architecture of the Trident processor, which tries to overcome these constraints and to satisfy the requirement of future applications. In addition, this book proposes the use of a multi-level instruction set architecture (ISA) to express fine-grain data parallelism to the Trident processor instead of using a huge transistor budget to dynamically extract it. Since the fundamental data structures for a wide variety of data parallel applications are scalar, vector, and matrix, our proposed Trident processor extends a scalar ISA with vector and matrix instruction sets to effectively process data parallel applications. Like vector microarchitectures, the Trident processor consists of a set of parallel lanes (each lane contains a set of vector pipelines and a slice of a register file) combined with a fast scalar core. However, the Trident processor can effectively process on parallel lanes not only vector but also matrix data.…