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Formal Equivalence Checking and Design Debugging Covers the topics of logic equivalence checking and design debugging in design verification. This book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. It also gives a survey of the literature on design error diagnosis and design error correction.
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- ÉditeurSpringer
- Date d'édition1998
- ISBN 10 079238184X
- ISBN 13 9780792381846
- ReliureRelié
- Nombre de pages229
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Formal Equivalence Checking and Design Debugging
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Springer US Jun 1998
(1998)
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Description du livre Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley 252 pp. Englisch. N° de réf. du vendeur 9780792381846
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Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing) by Shi-Yu Huang, Kwang-Ting (Tim) Cheng [Hardcover ]
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Description du livre Hardcover. Etat : new. N° de réf. du vendeur 9780792381846
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Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing, 12)
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Description du livre Etat : New. N° de réf. du vendeur ABLIING23Feb2416190185086
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Formal Equivalence Checking and Design Debugging
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Description du livre Etat : New. N° de réf. du vendeur 269396-n
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Description du livre Etat : New. PRINT ON DEMAND Book; New; Fast Shipping from the UK. No. book. N° de réf. du vendeur ria9780792381846_lsuk
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Formal Equivalence Checking and Design Debugging
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Description du livre Gebunden. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and . N° de réf. du vendeur 5970738
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Formal Equivalence Checking and Design Debugging
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(1998)
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ISBN 13 : 9780792381846
Neuf
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Description du livre Buch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley. N° de réf. du vendeur 9780792381846
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Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing, 12)
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Formal Equivalence Checking and Design Debugging
Edité par
Kluwer Academic Publishers
(1998)
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Description du livre Etat : New. Covers the topics of logic equivalence checking and design debugging in design verification. This book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. It also gives a survey of the literature on design error diagnosis and design error correction. Series: Frontiers in Electronic Testing. Num Pages: 247 pages, biography. BIC Classification: UM. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 15. Weight in Grams: 1170. . 1998. Hardback. . . . . Books ship from the US and Ireland. N° de réf. du vendeur V9780792381846
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EUR 421,52
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Formal Equivalence Checking and Design Debugging
Edité par
Kluwer Academic Publishers
(1998)
ISBN 10 : 079238184X
ISBN 13 : 9780792381846
Neuf
Couverture rigide
Quantité disponible : 15
Vendeur :
Evaluation vendeur
Description du livre Etat : New. Covers the topics of logic equivalence checking and design debugging in design verification. This book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. It also gives a survey of the literature on design error diagnosis and design error correction. Series: Frontiers in Electronic Testing. Num Pages: 247 pages, biography. BIC Classification: UM. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 15. Weight in Grams: 1170. . 1998. Hardback. . . . . N° de réf. du vendeur V9780792381846
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EUR 483,96
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