Rabab ezz eldin (23 résultats)

Etat : New.

Taschenbuch. Etat : Neu. High-Performance and Low-Power Network on Chip Switch | Network on Chip | Rabab Ezz-Eldin (u. a.) | Taschenbuch | Englisch | LAP Lambert Academic Publishing | EAN 9783848401451 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.…

Etat : New. In English.

Etat : New. In English.

Etat : New. pp. 300.

Etat : New. pp. 141.

Paperback. Etat : Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Paperback. Etat : Brand New. reprint edition. 164 pages. 9.25x6.10x0.37 inches. In Stock.

Hardcover. Etat : Brand New. 9.25x6.25x0.50 inches. In Stock.

Taschenbuch. Etat : Neu. Analysis and Design of Networks-on-Chip Under High Process Variation | Rabab Ezz-Eldin (u. a.) | Taschenbuch | xxi | Englisch | 2019 | Springer | EAN 9783319798370 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu. …

Etat : new. Questo è un articolo print on demand.

Etat : new. Questo è un articolo print on demand.

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Low leakage power switch is proposed to allow saving in power dissipation of the Network on Chip (NoC). Two power reduction techniques are exploited to design the proposed switch. The proposed NoC switch employs power supply gating to reduce the power dissipation. Adaptive virtual channel (AVC) is proposed as a novel technique to reduce power dissipation of the NoC switch. AVC technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating reduces the average leakage power consumption of proposed switch. The proposed techniques reduce the leakage and dynamic power dissipation of the switch.…

Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. 164 pp. Englisch.…

Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. 164 pp. Englisch.…

Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Demonstrates the impact of process variation on Networks-on-Chipof different topologiesIncludes an overview of the synchronous clocking scheme, clockdistribution network, main building blocks in asynchronous NoC design,handshake protocols, data en.…

Gebunden. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Demonstrates the impact of process variation on Networks-on-Chipof different topologiesIncludes an overview of the synchronous clocking scheme, clockdistribution network, main building blocks in asynchronous NoC design,handshake protocols, data en.…

Etat : New. Print on Demand pp. 300.

Etat : New. Print on Demand pp. 141.

Etat : New. PRINT ON DEMAND pp. 300.

Etat : New. PRINT ON DEMAND pp. 141.

Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 164 pp. Englisch.…

Buch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 164 pp. Englisch. …