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Ajouter au panierhardcover. Etat : Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority!
Vendeur : Patrico Books, Apollo Beach, FL, Etats-Unis
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Vendeur : Solr Books, Lincolnwood, IL, Etats-Unis
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Vendeur : HPB-Red, Dallas, TX, Etats-Unis
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Ajouter au panierHardcover. Etat : Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority!
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
EUR 111,96
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Ajouter au panierEtat : New. In.
Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
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Vendeur : GreatBookPricesUK, Woodford Green, Royaume-Uni
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Vendeur : Buchpark, Trebbin, Allemagne
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Ajouter au panierEtat : Sehr gut. Zustand: Sehr gut | Seiten: 352 | Sprache: Englisch | Produktart: Bücher | Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.
Vendeur : HPB-Red, Dallas, TX, Etats-Unis
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Ajouter au panierpaperback. Etat : Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority!
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
EUR 135,65
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Ajouter au panierEtat : New. In.
Vendeur : moluna, Greven, Allemagne
EUR 118,64
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Ajouter au panierGebunden. Etat : New. Covers the latest research that has been carried on in the area of thermal and power management of integrated circuits with emphasis on performance and reliability of ICs at system and circuit levelNo book provides cohesive treatment of the materi.
Vendeur : Books Puddle, New York, NY, Etats-Unis
EUR 171,58
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Ajouter au panierEtat : New. pp. 352 2nd Edition.
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
EUR 158,94
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Ajouter au panierEtat : New. In.
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
EUR 109,94
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Ajouter au panierTaschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - In Thermal and Power Management of Integrated Circuits, power and thermal management issues in integrated circuits during normal operating conditions and stress operating conditions are addressed. Thermal management in VLSI circuits is becoming an integral part of the design, test, and manufacturing. Proper thermal management is the key to achieve high performance, quality and reliability. Performance and reliability of integrated circuits are strong functions of the junction temperature. A small increase in junction temperature may result in significant reduction in the device lifetime.This book reviews the significance of the junction temperature as a reliability measure under nominal and burn-in conditions. The latest research in the area of electro-thermal modeling of integrated circuits will also be presented. Recent models and associated CAD tools are covered and various techniques at the circuit and system levels are reviewed. Subsequently, the authors provide an insight into the concept of thermal runaway and how it may best be avoided. A section on low temperature operation of integrated circuits concludes the book.
Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
EUR 175,53
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Ajouter au panierEtat : New.
Vendeur : GreatBookPricesUK, Woodford Green, Royaume-Uni
EUR 158,93
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Ajouter au panierEtat : New.
Vendeur : Majestic Books, Hounslow, Royaume-Uni
EUR 179,69
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Ajouter au panierEtat : New. pp. 352 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
EUR 171,13
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Ajouter au panierEtat : New. In.
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
EUR 171,16
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Ajouter au panierEtat : New. In.
Vendeur : Buchpark, Trebbin, Allemagne
EUR 81,94
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Ajouter au panierEtat : Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.
Vendeur : Buchpark, Trebbin, Allemagne
EUR 81,94
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Ajouter au panierEtat : Hervorragend. Zustand: Hervorragend | Sprache: Englisch | Produktart: Bücher | As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.
Vendeur : GreatBookPricesUK, Woodford Green, Royaume-Uni
EUR 175,36
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Ajouter au panierEtat : As New. Unread book in perfect condition.
Vendeur : Buchpark, Trebbin, Allemagne
EUR 94,63
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Ajouter au panierEtat : Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Thermal modeling of high performance circuits and systems is a crucial component for thermal and power management. The VLSI community is currently lacking a methodology to model and estimate junction temperature at any level of design other than low-level (transistor-level) circuits. The accuracy of thermal modeling has a substantial effect on the accuracy of thermal-management studies at the architectural level. Without this essential modeling capability, architecture researchers are limited to inaccurate estimation techniques, which are not suitable for thermal management of integrated circuits.In Thermal and Power Management of Integrated Circuits, power and thermal management issues in integrated circuits during normal operating conditions and stress operating conditions are addressed. Thermal management in VLSI circuits is becoming an integral part of the design, test, and manufacturing. Proper thermal management is the key to achieve high performance, quality and reliability. Performance and reliability of integrated circuits are strong functions of the junction temperature. A small increase in junction temperature may result in significant reduction in the device lifetime.This book reviews the significance of the junction temperature as a reliability measure under nominal and burn-in conditions. The latest research in the area of electro-thermal modeling of integrated circuits will also be presented. Recent models and associated CAD tools are covered and various techniques at the circuit and system levels are reviewed. Subsequently, the authors provide an insight into the concept of thermal runaway and how it may best be avoided. A section on low temperature operation of integrated circuits concludes the book.
Vendeur : Mispah books, Redhill, SURRE, Royaume-Uni
EUR 175,16
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Ajouter au panierPaperback. Etat : Like New. Like New. book.
Vendeur : GreatBookPricesUK, Woodford Green, Royaume-Uni
EUR 192,90
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Ajouter au panierEtat : As New. Unread book in perfect condition.
Vendeur : Mispah books, Redhill, SURRE, Royaume-Uni
EUR 183,44
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Ajouter au panierHardcover. Etat : Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
EUR 216,17
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Ajouter au panierEtat : As New. Unread book in perfect condition.
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
EUR 218,47
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Ajouter au panierEtat : New. In.
Vendeur : Buchpark, Trebbin, Allemagne
EUR 127,49
Quantité disponible : 2 disponible(s)
Ajouter au panierEtat : Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Keine Beschreibung verfügbar.